erreur dans le code

**emnag** · 24/10/2010, 01h16

j'ai écrit un programme sous EDK application software en embarqué
qui permet de lire l’état d'un bouton poussoir et afficher le résultat sue une LED
j'ai compilé le programme
une erreur existe pour la fonction XGpio_mGetDataReg

/cygdrive/c/VIRTEX4/application/soucesC/main.c: In function ‘main’:
/cygdrive/c/VIRTEX4/application/soucesC/main.c:30: error: expected expression before ‘;’ token
/cygdrive/c/VIRTEX4/application/soucesC/main.c:40:2: warning: no newline at end of file
make: *** [lab_test/executable.elf] Error 1

aidez moi pour corriger cette erreur

Code :

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#include "xparameters.h"
 
#include "stdio.h"
 
#include "xbasic_types.h"
 
#include "xgpio_l.h"
 
#include "xutil.h"
 
 
/*****************************************************************************/
 #define XGpio_mSetDataDirection(BaseAddress, Channel, DirectionMask)
/*****************************************************************************/
/*****************************************************************************/
#define XGpio_mGetDataReg(BaseAddress, Channel) 
/****************************************************************************//*****************************************************************************/
#define XGpio_mSetDataReg(BaseAddress, Channel, Data) 
/****************************************************************************/
 
//====================================================
Xuint32 Push_Read;
int main (void) {
Xuint32 Push_Read;
		print("--Entering main --\r\n");
XGpio_mSetDataDirection(XPAR_LEDS_4BIT_BASEADDR, 1, 0*00000000);
 
while (1) {
 
Push_Read = XGpio_mGetDataReg(XPAR_Push_button_S_BASEADDR, 1);
 
if (Push_Read == 0*00000001) {
XGpio_mSetDataReg(XPAR_LEDS_4BIT_BASEADDR, 1, 0*0000000F);
}
else {
XGpio_mSetDataReg(XPAR_LEDS_4BIT_BASEADDR, 1, 0*00000000);
}
}
return 0;
}

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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 12.1 EDK_MS1.53d
* DO NOT EDIT.
*
* Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
 
* 
* Description: Driver parameters
*
*******************************************************************/
 
#define STDIN_BASEADDRESS 0x84000000
#define STDOUT_BASEADDRESS 0x84000000
 
/******************************************************************/
 
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 2
 
/* Definitions for peripheral LEDS_4BIT */
#define XPAR_LEDS_4BIT_BASEADDR 0x81420000
#define XPAR_LEDS_4BIT_HIGHADDR 0x8142FFFF
#define XPAR_LEDS_4BIT_DEVICE_ID 0
#define XPAR_LEDS_4BIT_INTERRUPT_PRESENT 0
#define XPAR_LEDS_4BIT_IS_DUAL 0
 
 
/* Definitions for peripheral PUSH_BUTTON_S */
#define XPAR_PUSH_BUTTON_S_BASEADDR 0x81400000
#define XPAR_PUSH_BUTTON_S_HIGHADDR 0x8140FFFF
#define XPAR_PUSH_BUTTON_S_DEVICE_ID 1
#define XPAR_PUSH_BUTTON_S_INTERRUPT_PRESENT 0
#define XPAR_PUSH_BUTTON_S_IS_DUAL 0
 
 
/******************************************************************/
 
/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1
 
/* Definitions for peripheral RS232_UART */
#define XPAR_RS232_UART_BASEADDR 0x84000000
#define XPAR_RS232_UART_HIGHADDR 0x8400FFFF
#define XPAR_RS232_UART_DEVICE_ID 0
#define XPAR_RS232_UART_BAUDRATE 9600
#define XPAR_RS232_UART_USE_PARITY 0
#define XPAR_RS232_UART_ODD_PARITY 0
#define XPAR_RS232_UART_DATA_BITS 8
 
 
/******************************************************************/
 
 
/* Canonical definitions for peripheral RS232_UART */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_UARTLITE_0_HIGHADDR 0x8400FFFF
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN -1
 
 
/******************************************************************/
 
 
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_0 */
#define XPAR_XPS_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
#define XPAR_XPS_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
 
 
/******************************************************************/
 
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 1
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
 
/* Definitions for peripheral XPS_INTC_0 */
#define XPAR_XPS_INTC_0_DEVICE_ID 0
#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
#define XPAR_XPS_INTC_0_HIGHADDR 0x8180FFFF
#define XPAR_XPS_INTC_0_KIND_OF_INTR 0xFFFFFFFF
 
 
/******************************************************************/
 
#define XPAR_INTC_SINGLE_BASEADDR 0x81800000
#define XPAR_INTC_SINGLE_HIGHADDR 0x8180FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID
#define XPAR_XPS_TIMER_0_INTERRUPT_MASK 0X000001
#define XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR 0
 
/******************************************************************/
 
/* Canonical definitions for peripheral XPS_INTC_0 */
#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_INTC_0_HIGHADDR 0x8180FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFF
 
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR
 
/******************************************************************/
 
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1
 
/* Definitions for peripheral XPS_TIMER_0 */
#define XPAR_XPS_TIMER_0_DEVICE_ID 0
#define XPAR_XPS_TIMER_0_BASEADDR 0x83C00000
#define XPAR_XPS_TIMER_0_HIGHADDR 0x83C0FFFF
 
 
/******************************************************************/
 
/* Canonical definitions for peripheral XPS_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_0_DEVICE_ID
#define XPAR_TMRCTR_0_BASEADDR 0x83C00000
#define XPAR_TMRCTR_0_HIGHADDR 0x83C0FFFF
 
 
/******************************************************************/
 
/* Definitions for bus frequencies */
#define XPAR_CPU_PPC405_DPLB0_FREQ_HZ 100000000
#define XPAR_CPU_PPC405_IPLB0_FREQ_HZ 100000000
/******************************************************************/
 
/* Canonical definitions for bus frequencies */
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
/******************************************************************/
 
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000
#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 100000000
 
/******************************************************************/
 
#define XPAR_CPU_ID 0
#define XPAR_PPC405_VIRTEX4_ID 0
#define XPAR_PPC405_VIRTEX4_DPLB0_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB0_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_FASTEST_PLB_CLOCK DPLB0
#define XPAR_PPC405_VIRTEX4_GENERATE_PLB_TIMESPECS 1
#define XPAR_PPC405_VIRTEX4_DPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_DPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_IPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100
#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x000001FF
#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1
#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1
#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0
#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1
#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000
#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000
#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000
#define XPAR_PPC405_VIRTEX4_HW_VER "2.01.b"
 
/******************************************************************/

erreur dans le code

C

Mode arborescent

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