1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
|
library ieee;
use ieee.std_logic_1164.all;
entity exsimple is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : out std_logic);
end exsimple;
architecture BEHAVIORAL of exsimple is
attribute BOX_TYPE : STRING ;
signal S1 : std_logic;
component XOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
begin
BLOC1 : XOR2
port map (I0=>B, I1=>A, O=>S1);
BLOC2 : AND2
port map (I0=>C, I1=>S1, O=>D);
end BEHAVIORAL; |
Partager