PLLDIV 96MHz PLL Prescaler No Divide 4MHzinput
CPUDIV CPU System Clock Postscaler [OSC1/OSC2 Src: /1][96MHz PLL Src: /2]
USBPLL Full-Speed USB Clock Source Selection Clock src from OSC1/OSC2
OSC Oscillator INTOSC: INTOSC +RA6, USB EC
FCMEN Fail-Safe Clock Monitor Enable Disable
IESO Internal External Switch Over Mode Disabled
PUT Power Up Timer Disabled
BODEN Brown Out Detect Enabled in hardware, SBOREN disabled
BODENV Brown Out Voltage 2.0V
VREGEN USB Voltage Regulator Disabled
WDT Watchdog Timer Disabled-Controlled by SWDTEN bit
WDTPS Watchdog Postscaler 1:32768
PBADEN PortB A/D Enable PORTB<4:0> configured as analog inputs on RESET
LPT1OSC Low Power Timer1 Osc enable Disabled
MCLRE Master Clear Enable MCLR Enabled,RE3 Disabled
STVR Stack Overflow Reset Disabled
LVP Low Voltage Program Disabled
BBSIZ Boot Block Size Select 1 KW
ENICPORTDedicated In-Circuit Port {ICD/ICSP}Enabled
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