Détecteur de passage

Bonsoir, je travaille actuellement sur un programme pour un TP et j'ai souhaité le préparer chez moi, j'ai donc réaliser un programme mais il me donne pas mal d'erreurs, j'y ai réfléchi et j'ai fais des recherches sur internet mais je n'ai trouvé aucune solution. J'aimerai comprendre ce qui ne va pas.

Voila le code :

Code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity E_Passage is
    Port ( S : in  STD_LOGIC_VECTOR (1 downto 0);
           CLK : in  STD_LOGIC;
           ID : out  STD_LOGIC;
           C : buffer  STD_LOGIC);
end E_Passage; 
 
architecture A_Passage of E_Passage is
  Signal Q:STD_LOGIC_VECTOR (2 downto 0):="000";
begin
  process(CLK)
  begin
    if CLK'event and CLK='1' then
      case Q is
 
        when "000" =>
          if S1='1' and S2='0' then
            Q<="001";
          else if S1='0' and S2='1' then
            Q<="010";
          else
            Q<="000";
          end if;
 
        when "001" =>
          if S1='0' and S2='0' then
            Q<="011";
          else
            Q<="001";
          end if;
 
        when "010" =>
          if S1='0' and S2='0' then
            Q<="011";
          else
            Q<="010";
          end if;
 
        when "011" =>
          if S1='1' and S2='0' then
            Q<="100";
          else if S1='0' and S2='1' then
            Q<="101";
          else 
            Q<="011";
          end if;
 
        when "100" =>
          if S1='1' and S2='1' then
            Q<="110";
          else
            Q<="100";
          end if;
 
        when "101" =>
          if S1='1' and S2='1' then 
            Q<="111";
          else
            Q<="101";
          end if;
 
        when "110" =>
          if S1='1' and S2='1' then
            Q<="000"
          end if;
 
        when "111" =>
          if S1='1' and S2='1' then
            Q<="000";
          end if;
 
      end case;
 
    end if;
 
  end process;
 
  ID <='1' when Q="110" else
       '0';
 
  C<='1' when Q="110" else
     '1' when Q="111" else
    '0';
 
end A_Passage;

et Voila les erreurs:

ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 58: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 65: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 72: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 81: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 88: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 95: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 98: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 105: Syntax error near "case".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 109: Syntax error near "process".
ERROR:HDLCompiler:806 - "C:/Users/Benda/Desktop/PASSAGE/Passage/E_Passage.vhd" Line 118: Syntax error near "A_Passage".
ERROR: ProjectMgmt - 10 error(s) found while parsing design hierarchy.

Merci d'avance.