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| library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY clk_div IS
PORT
(
clock_27Mhz : IN STD_LOGIC;
reset : IN STD_LOGIC;
clock_1MHz : OUT STD_LOGIC;
clock_100KHz : OUT STD_LOGIC;
clock_10KHz : OUT STD_LOGIC;
clock_1KHz : OUT STD_LOGIC;
clock_100Hz : OUT STD_LOGIC;
clock_10Hz : OUT STD_LOGIC;
clock_1Hz : OUT STD_LOGIC);
END clk_div;
ARCHITECTURE a OF clk_div IS
SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL count_100Khz, count_10Khz, count_1Khz,count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clock_27Mhz,reset)
BEGIN
-- Divise par 27
IF reset = '0' THEN
count_1Mhz <= (others => '0');
count_100Khz <= (others => '0');
count_10Khz <= (others => '0');
count_1Khz <= (others => '0');
count_100hz <= (others => '0');
count_10hz <= (others => '0');
count_1hz <= (others => '0');
ELSIF rising_edge (clock_27Mhz) THEN
IF count_1Mhz < 26 THEN
count_1Mhz <= count_1Mhz + 1;
ELSE
count_1Mhz <= (others => '0');
IF count_100khz < 9 THEN
count_100khz <= count_100khz + 1;
ELSE
count_100khz <= (others => '0') ;
IF count_10khz < 9 THEN
count_10khz <= count_10khz + 1;
ELSE
count_10khz <= (others => '0') ;
IF count_1khz < 9 THEN
count_1khz <= count_1khz + 1;
ELSE
count_1khz <= (others => '0') ;
IF count_100hz < 9 THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= (others => '0') ;
IF count_10hz < 9 THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= (others => '0') ;
IF count_1hz < 9 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= (others => '0') ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
IF count_1Mhz < 13 THEN
clock_1Mhz <= '0';
ELSE
clock_1Mhz <= '1' ;
END IF;
IF count_100khz < 5 THEN
clock_100Khz <= '0';
ELSE
clock_100Khz <= '1' ;
END IF;
IF count_10khz < 5 THEN
clock_10Khz <= '0';
ELSE
clock_10Khz <= '1' ;
END IF;
IF count_1khz < 5 THEN
clock_1Khz <= '0';
ELSE
clock_1Khz <= '1' ;
END IF;
IF count_100hz < 5 THEN
clock_100hz <= '0';
ELSE
clock_100hz <= '1' ;
END IF;
IF count_10hz < 5 THEN
clock_10hz <= '0';
ELSE
clock_10hz <= '1' ;
END IF;
IF count_1hz < 5 THEN
clock_1hz <= '0';
ELSE
clock_1Khz <= '1' ;
END IF;
END IF;
END PROCESS;
END a; |
