Code de FIR

Bonjour

J'ai écrit un code VHDL de filtre FIR mais le soucis est au niveau du testbench bien que le port data_in prend ses valeurs d'un fichier en simulation c'est tjrs 0 donc la lecture du fichier ne marche pas :

Code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use ieee.numeric_std.all;
 
 
entity fir2 is
generic(
      word_size : integer:=16);
port ( clk,shift : in std_logic;
		 rst : in std_logic;
		 clear : in std_logic;
		 data_in : in std_logic_vector ( word_size-1 downto 0);
		 data_out : out std_logic_vector ( word_size-1 downto 0);
		 s1,s2: in std_logic_vector (3 downto 0));
end fir2;
 
architecture Behavioral of fir2 is
 
component DFF2
generic ( N: integer:=16);
    Port ( clk,rst,clear,shift : in  STD_LOGIC;
				d : in STD_LOGIC_VECTOR ( N-1 downto 0);
           q : out  STD_LOGIC_VECTOR ( N-1 downto 0));
end component;
 
component Mutiplexer
port( s : in std_logic_vector (3 downto 0);
		x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17 : in std_logic_vector (15 downto 0);
		y1,y2 : out std_logic_vector (15 downto 0));
end component;
 
component adder
	GENERIC(
		N : INTEGER := 32);
	PORT(
	   	x1 : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		x2 : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
	   	y : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0));
END component;
 
component multiplier
  GENERIC (
    N : integer := 16);
  PORT(
	   	x1 : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		x2 : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
	   	y : OUT STD_LOGIC_VECTOR(2*N-1 DOWNTO 0));
END component;
 
component DFF
generic ( N: integer:=16);
    Port ( clk,rst,clear : in  STD_LOGIC;
				d : in STD_LOGIC_VECTOR ( 2*N-1 downto 0);
           q : out  STD_LOGIC_VECTOR ( 2*N-1 downto 0));
end component;
 
TYPE coeff is array(0 to 16) of std_logic_vector(15 downto 0);
TYPE regis is array(0 to 17) of std_logic_vector(15 downto 0);
 
signal f:coeff;
signal reg:regis;
signal regmult1,regmult2: std_logic_vector (31 downto 0);--register to store the output of the multiplier
signal regadd1,regadd2 : std_logic_vector (31 downto 0);--register to store the output of the adder
signal add11,add12,add21,add22: std_logic_vector (31 downto 0);-- signals in the inputs and the output of the adder
signal nul,multi11,multi12,multi21,multi22 : std_logic_vector (15 downto 0);-- signals in the inputs of the multiplier
 
begin
 
f(0)<=conv_STD_LOGIC_VECTOR(-282,16);
f(1)<=conv_STD_LOGIC_VECTOR(-369,16);
f(2)<=conv_STD_LOGIC_VECTOR(-307,16);
f(3)<=conv_STD_LOGIC_VECTOR(-67,16);
f(4)<=conv_STD_LOGIC_VECTOR(326,16);
f(5)<=conv_STD_LOGIC_VECTOR(803,16);
f(6)<=conv_STD_LOGIC_VECTOR(1259,16);
f(7)<=conv_STD_LOGIC_VECTOR(1587,16);
f(8)<=conv_STD_LOGIC_VECTOR(1706,16);
f(9)<=conv_STD_LOGIC_VECTOR(1587,16);
f(10)<=conv_STD_LOGIC_VECTOR(1259,16);
f(11)<=conv_STD_LOGIC_VECTOR(803,16);
f(12)<=conv_STD_LOGIC_VECTOR(326,16);
f(13)<=conv_STD_LOGIC_VECTOR(-67,16);
f(14)<=conv_STD_LOGIC_VECTOR(-307,16);
f(15)<=conv_STD_LOGIC_VECTOR(-369,16);
f(16)<=conv_STD_LOGIC_VECTOR(-282,16);
 
nul<="0000000000000000";
 
reg(0)<=data_in;
 
loopy1:for i in 0 to 16 generate
uut1:DFF2 port map(d=>reg(i),q=>reg(i+1),clk=>clk,clear=>clear,rst=>rst,shift=>shift);
end generate;
 
uutmu1coeff:mutiplexer port map(x0=>f(0),x1=>nul,x2=>f(2),x3=>f(1),x4=>f(4),x5=>f(3),x6=>f(6),x7=>f(5),x8=>f(8),x9=>f(7),x10=>f(10),x11=>f(9),x12=>f(12),x13=>f(11),x14=>f(14),x15=>f(13),x16=>f(16),x17=>f(15),s=>s1,y1=>multi11,y2=>multi21);
 
uutmu2:mutiplexer port map(x0=>nul,x1=>reg(1),x2=>reg(2),x3=>reg(3),x4=>reg(4),x5=>reg(5),x6=>reg(6),x7=>reg(7),x8=>reg(8),x9=>reg(9),x10=>reg(10),x11=>reg(11),x12=>reg(12),x13=>reg(13),x14=>reg(14),x15=>reg(15),x16=>reg(16),x17=>reg(17),s=>s2,y1=>multi12,y2=>multi22);	
 
uutmultip1:multiplier port map(x1=>multi11,x2=>multi12,y=>regmult1);
 
uutmultip2:multiplier port map(x1=>multi21,x2=>multi22,y=>regmult2);
 
uutreg1:DFF port map(clk=>clk,rst=>rst,clear=>clear,d=>regmult1,q=>add11);
 
uutreg2:DFF port map(clk=>clk,rst=>rst,clear=>clear,d=>regmult2,q=>add12);
 
uutadd1:adder port map(x1=>add11,x2=>add12,y=>regadd1);  
 
uutreg3:DFF port map(clk=>clk,rst=>rst,clear=>clear,d=>regadd1,q=>add21);
 
uutadd2:adder port map(x1=>add21,x2=>add22,y=>regadd2); 
 
uutreg4:DFF port map(clk=>clk,rst=>rst,clear=>clear,d=>regadd2,q=>add22);
 
data_out<=regadd2 (28 downto 13); 
 
 
end Behavioral;

Testbench :

Code:

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
 
library std;
use std.textio.all;
 
---------------------------------------------------------------------------------------------------
 
entity fir_tb is
 
end fir_tb;
 
---------------------------------------------------------------------------------------------------
 
architecture fir2 of fir_tb is
 
  component fir2
    generic(
      word_size : integer
      );      
    port (
      clk, rst, clear,shift      : in  std_logic;
		s1,s2						: in std_logic_vector(3 downto 0);
      data_in              : in  std_logic_vector(word_size-1 downto 0);
      data_out             : out std_logic_vector(word_size-1 downto 0)
      );
  end component;
 
 
  -- period
  constant input_period : time    := 10 ns;
  constant period       : time    := 145 ns;
  constant word_size    : integer := 16;
 
 
  -- component ports
  signal rst, clear,shift              : std_logic;
  signal s1,s2							: std_logic_vector (3 downto 0);
  signal data_in                 : std_logic_vector(word_size-1 downto 0);
  signal data_out                : std_logic_vector(word_size-1 downto 0);
  -- clock
  signal clk                     : std_logic := '1';
 
 
 
begin  -- fir
 
 
  -- instantiation
  ufir: fir2
    generic map (
      word_size => word_size)
    port map (
      clk      => clk,
		shift    => shift,
      rst      => rst,
      clear    => clear,
		s1       => s1,
		s2       => s2,
      data_in  => data_in,
      data_out => data_out);
 
  -- clock generation
  Clk <= not Clk after input_period/2;
 
  -- waveform generation
  WaveGen_Proc : process
    -- file input
    file sample : text is in "./fir_input.txt";
    file res    : text is out "./fir_output.txt";
 
    variable ptr  : line;
    variable data : integer;
 
  begin
 
    -- reset/clear
    rst <= '1';
    clear  <= '1';
    wait for period;
    rst <= '0';
    clear <= '0';
 
    -- samples uploading/downloading
		shift<='1';
		while not(endfile(sample)) loop
      readline(sample, ptr);
      read(ptr, data);
      -- assigning input
      data_in <= conv_std_logic_vector(data, word_size);
		shift<='1';
		wait for 2*input_period;
		shift<='0';
		wait for input_period;
		s1<="0000";
		s2<="1001";
		wait for input_period;
		s1<="0001";
		s2<="1000";
		wait for input_period;
		s1<="0010";
		s2<="0111";
		wait for input_period;
		s1<="0011";
		s2<="0110";
		wait for input_period;
		s1<="0100";
		s2<="0101";
		wait for input_period;
		s1<="0101";
		s2<="0100";
		wait for input_period;
		s1<="0110";
		s2<="0011";
		wait for input_period;
		s1<="0111";
		s2<="0010";
		wait for input_period;
		s1<="1000";
		s2<="0001";
		wait for input_period;
		s2<="0000";
		s1<="1001";
		wait for input_period;
			-- writing output
      data    := conv_integer(data_out);
      write(ptr, data);
      writeline(res, ptr);
      wait for input_period;
    end loop;
 
    assert true report "Simulation Ended" severity note;
    -- that's all folks
    wait for period;
 
 
  end process WaveGen_Proc;
 
end fir2;

MERCI D'AVANCE