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| library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std;
use ieee.std_logic_arith.all;
ENTITY NOC is
generic
(
Xlocal : std_logic_vector(1 downto 0):="01";
Ylocal : std_logic_vector(1 downto 0):="01");
port (clk, RESET: IN std_logic;
SN8, SS8, SE8, SO8 : OUT std_logic_vector(7 downto 0);
EN8, ES8, EE8, EO8 : OUT std_logic_vector(7 downto 0);
msg_x,msg_y : std_logic_vector(1 downto 0);
Snord, Ssud, Sest, Souest: OUT std_logic;
Enord, Esud, Eest, Eouest : IN std_logic);
end NOC;
Architecture ex OF NOC is
SIGNAL X_msg,Y_msg: std_logic_vector(1 downto 0);
begin
-- - - - - - - - - - - - - - - - - - - - - - -
X :process (clk)
begin
X_msg <= msg_x;
if (clk'event and clk='1')then
if(Xlocal < X_msg) then
Sest <='1';
Souest <='0';
elsif (Xlocal > X_msg) then
Souest <='1';
Sest <='0';
else
Sest <='0';
Souest <='0';
end if;
end if;
end process;
-- - - - - - - - - - - - - - - - - - - - - - -
Y :process (clk)
begin
Y_msg <= msg_y;
if (clk'event and clk='1')then
if(Ylocal < Y_msg) then
Snord <='1';
Ssud <='0';
elsif (Ylocal > Y_msg) then
Ssud <='1';
Snord <='0';
else
Snord <='0';
Ssud <='0';
end if;
end if;
end process;
end ex; |
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