Discussion :

[manou756011]

bonjour s'il vous plait aidez moi à corriger ce code
voici l'image de ce calculateur :

Code :

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:19:06 04/21/2014 
-- Design Name: 
-- Module Name:    calculateur - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity calculateur is
port(
clk,rst,ok ,suiv: in std_logic;
note_paye: out std_logic_vector( 4 downto 0)
);
end calculateur;
architecture Behavioral of calculateur is
signal sig1: std_logic ; 
signal sig3: std_logic ;
signal sig4: std_logic_vector( 2 downto 0);
signal note_cr: std_logic_vector( 8 downto 0 ) ;
signal fin : std_logic;
component mae 
port(
clk,rst:in std_logic;
ok,nex:in std_logic;
sel,inc,raz: out std_logic
);
end component;
component note_critere
generic( n : integer := 9);
port(
clk,raz,inc: in std_logic;
cpt: in std_logic_vector(2 downto 0);
S: inout std_logic_vector( n-1 downto  0 )
);
end component;
component compteur
port(
raz,clk,SEL:in std_logic ;
D : in std_logic_vector ( 2 downto 0 ); 
cpt: out std_logic_vector( 2 downto 0) 
);
end component;
component note_pays
generic( p : integer := 21 );
port(
sel,CLK ,RAZ :in std_logic; 
note_critere: in std_logic_vector( 8 downto 0);
n_p:inout std_logic_vector( p-1 downto 0)
);
end component;
begin
comp1: mae  
port map( clk=>clk , ok=>ok , nex=>suiv , inc=>sig1 , rst=>rst ,sel=>sig3);
comp2: note_critere 
generic map(4) 
port map(clk=>clk , inc=>sig1, raz=>rst, cpt=>sig4 , S => note_cr);
comp3: compteur 
port map( clk=>clk , raz=>rst ,SEL=>sig3, cpt=>sig4,D=>sig3 );	
comp4: note_pays 
generic map(5) 
port map(CLK=>clk,sel=>sig3,RAZ=>rst,note_critere => note_cr ,n_p=>note_paye );
end Behavioral;