Perdu dans des problèmes de synchronisation

**binome-x** · 13/07/2016, 12h21

Bonjour,
je n'arrive pas à comprendre un truc. Je commence par vous donner le code de mon composant :

Code :

Sélectionner tout - Visualiser dans une fenêtre à part

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
library ieee; 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity filter is 
  generic(
    img_width : integer := 4;
    blk_width : integer := 2;
    img_length : integer := 4;
    blk_length : integer := 2;
    data_size : integer := 12;      -- pixel size
    address_size1 : integer := 4;   -- row*column size
    address_size2 : integer := 2;   -- row size
    address_size3 : integer := 2    -- column size
    );
  port(
    clock: in std_logic;
    a_reset_n: in std_logic; 																    	-- asynchronous reset low level 
    enable_main_program: in std_logic; 														-- this enable gives a possibility to the main programm to inhibit all the modules if there is an error 
    enable_pixel_in: in std_logic;  															-- enable the processing of the current pixel 
    pixel_in: in std_logic_vector(data_size-1 downto 0); 					-- current pixel
    enable_pixel_out: out std_logic;  													  -- enable the exit of the computed pixel 
    pixel_out : out std_logic_vector(data_size-1 downto 0) := (others => '0')       -- computed pixel
    );
end filter;
 
architecture rtl of filter is 
 
  component ram_mem is 
    generic (
      data_size : integer := data_size;
      address_size : integer := address_size2
      );
    port(
      clock: in std_logic;
      a_reset_n: in std_logic;
      enable_read: in std_logic; 
      enable_write: in std_logic; 
      address: in std_logic_vector(address_size-1 downto 0);
      data_in: in std_logic_vector(data_size-1 downto 0);
      data_out: out std_logic_vector(data_size-1 downto 0) := (others => '0')
      );
  end component ram_mem ;
 
  type machine is (s0, s1, s2, s3);                    -- 4 states because a new pixel is available each 4 cycles
  signal state : machine; 
 
  signal reset : std_logic;
 
  type enbl is array (2 downto 0) of std_logic;  -- memory(i) enable
  signal s_enable_w : enbl;
  signal s_enable_r : enbl;
 
  signal s_address : std_logic_vector(address_size2-1 downto 0):=(others => '0');
 
  type s_out is array (0 to 2) of std_logic_vector(data_size-1 downto 0);
  signal s_data_out : s_out := (others => (others => '0'));
 
  signal cntr_img_col : integer range 0 to 3 := 0;
  signal cntr_img_row : integer range 0 to 3 := 0;
  signal cntr_wmem : integer range 0 to 2 := 0;         -- actual write memory
 
  type blk_col is array (1 downto 0) of integer;
  type blk_all is array (1 downto 0) of blk_col;
  signal cur_blk : blk_all := (others => (others => 0)); -- current block
 
  signal sum : integer range 0 to (2**data_size)*4-1;  -- actual block sum
  signal p_enable_pixel_out : std_logic;
  signal first_img : std_logic := '1';
 
begin
 
  memory : for i in 0 to 2 generate
    mem : ram_mem
      generic map(
        data_size     => data_size,
        address_size  => address_size2)
      port map ( 
        clock => clock,
        a_reset_n => reset,
        enable_read => s_enable_r(i), 
        enable_write => s_enable_w(i), 
        address => s_address,
        data_in => pixel_in,
        data_out => s_data_out(i)
        );
  end generate memory;
 
  reset <= a_reset_n and enable_main_program;
 
  process (clock, reset)
  begin 
    if (reset='0') then 
      state <= s0;
      cntr_img_col <= 0;
      cntr_img_row <= 0;
      cntr_wmem <= 0;
      s_enable_r <= (others => '0');
      s_enable_w <= (others => '0');
      sum <= 0;
      cur_blk <= (others => (others => 0));
      enable_pixel_out <= '0';
      p_enable_pixel_out <= '0';
      first_img <= '1';
 
    elsif rising_edge(clock) then 
      case state is
        when s0 => 
          if(enable_pixel_in = '1') then -- a pixel is coming 
            s_address <= std_logic_vector(to_unsigned(cntr_img_col,address_size2)); 
            s_enable_w(cntr_wmem) <= '1';
            if first_img = '0' or cntr_img_row > 1 then
              for i in 0 to 2 loop
                if i=cntr_wmem then
                  s_enable_r(i) <= '0';
                else
                  s_enable_r(i) <= '1';
                end if;
              end loop;
            end if;
            enable_pixel_out <= '0';
            state <= s1;
          end if;
 
        when s1 =>
          s_enable_w <= (others => '0');
          state <= s2;
 
        when s2 =>
          s_enable_r <= (others => '0');
          if cntr_img_col = img_width-1 then
            cntr_img_col <= 0;
            if cntr_img_row = img_length-1 then
              cntr_img_row <= 0;
            else
              cntr_img_row <= cntr_img_row+1;
            end if;
            if cntr_wmem = 2 then
              cntr_wmem <= 0;
            else
              cntr_wmem <= cntr_wmem+1;
            end if;
          else
            cntr_img_col <= cntr_img_col+1;
          end if;
 
          cur_blk(0)(0) <= cur_blk(1)(0);
          cur_blk(0)(1) <= cur_blk(1)(1);
          if cntr_wmem=0 then
            cur_blk(1)(0) <= to_integer(unsigned(s_data_out(1)));
            cur_blk(1)(1) <= to_integer(unsigned(s_data_out(2)));
            sum <= sum+to_integer(unsigned(s_data_out(1)))+to_integer(unsigned(s_data_out(2)))-cur_blk(0)(0)-cur_blk(0)(1);
          elsif cntr_wmem=1 then
            cur_blk(1)(0) <= to_integer(unsigned(s_data_out(2)));
            cur_blk(1)(1) <= to_integer(unsigned(s_data_out(0)));
            sum <= sum+to_integer(unsigned(s_data_out(2)))+to_integer(unsigned(s_data_out(0)))-cur_blk(0)(0)-cur_blk(0)(1);
          else
            cur_blk(1)(0) <= to_integer(unsigned(s_data_out(0)));
            cur_blk(1)(1) <= to_integer(unsigned(s_data_out(1)));
            sum <= sum+to_integer(unsigned(s_data_out(0)))+to_integer(unsigned(s_data_out(1)))-cur_blk(0)(0)-cur_blk(0)(1);
          end if;
 
        state <= s3;
 
        when s3 =>
          pixel_out <= std_logic_vector(to_unsigned(sum/4, data_size));
          if cntr_img_col > 0 and cntr_img_row /= 1 and (first_img = '0' or cntr_img_row > 1) then
            p_enable_pixel_out <= '1';
          else
            p_enable_pixel_out <= '0';              
          end if;
          if p_enable_pixel_out = '1' then
            enable_pixel_out <= '1';
          end if;
          if cntr_img_row = img_length-1 and cntr_img_col = img_width-1 then
            first_img <= '0';
          end if;
          state <= s0;         
      end case;
    end if;
  end process; 
end rtl;

et de mon testbench :

Code :

Sélectionner tout - Visualiser dans une fenêtre à part

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
library ieee; 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tb_filter is
end tb_filter;
 
architecture test of tb_filter is
	component filter is
  generic(
    img_width : integer := 4;
    blk_width : integer := 2;
    img_length : integer := 4;
    blk_length : integer := 2;
    data_size : integer := 12;  
    address_size1 : integer := 4; 
    address_size2 : integer := 2; 
    address_size3 : integer := 2 
    );
  port(
    clock: in std_logic;
    a_reset_n: in std_logic; 						    											
    enable_main_program: in std_logic; 													
    enable_pixel_in: in std_logic;  															
    pixel_in: in std_logic_vector(data_size-1 downto 0);	
    enable_pixel_out: out std_logic; 				
    pixel_out : out std_logic_vector(data_size-1 downto 0);
    pixel_out_x : out std_logic_vector(address_size2-1 downto 0);
    pixel_out_y : out std_logic_vector(address_size3-1 downto 0)
    );
	end component filter;
 
    signal s_clock: std_logic := '1';
    signal s_a_reset_n: std_logic := '0';
    signal s_enable_in: std_logic := '0';
    signal s_enable_main_program : std_logic := '0';
    signal s_pixel_in : std_logic_vector(11 downto 0) := (others => '0');
    signal s_pixel_out : std_logic_vector(11 downto 0) := (others => '0');
    signal s_enable_pixel_out : std_logic;
    signal s_pixel_out_x : std_logic_vector(1 downto 0);
    signal s_pixel_out_y : std_logic_vector(1 downto 0);
 
begin
 
	comp : filter
  generic map(
    img_width => 4,
    blk_width => 2,
    img_length => 4,
    blk_length => 2,
    data_size => 12,      -- pixel size
    address_size1 => 4,   -- row*column size
    address_size2 => 2,   -- row size
    address_size3 => 2    -- column size
  )
	port map(	
    clock => s_clock,
    a_reset_n => s_a_reset_n,
    enable_main_program => s_enable_main_program,
    enable_pixel_in => s_enable_in,
    pixel_in => s_pixel_in,
    enable_pixel_out => s_enable_pixel_out,
    pixel_out => s_pixel_out,
    pixel_out_x => s_pixel_out_x,
    pixel_out_y => s_pixel_out_y
  );
 
  clock : process
  begin
    wait for 1 ns;
    s_clock <= not s_clock;
  end process;
 
  reset : process
  begin
    wait for 2 ns;
    s_a_reset_n <= '1';
    wait;
  end process;
 
  start : process
  begin
    wait for 6 ns;
    s_enable_main_program <='1';
    s_enable_in <= '1';
    wait;
  end process;
 
  test_vectors : process
  begin
    wait for 6 ns;
    for i in 0 to 15 loop
      s_pixel_in <= std_logic_vector(to_unsigned(i+1, 12));
      wait for 8 ns;
    end loop;
    wait;
  end process;
 
end test;

J'aimerais tout simplement que tout ce qui est fait dans l'état s2 de ma machine d'états soit fait dans s1. J'ai essayé de copier simplement les lignes 130 à 161 entre la 126 et la 127 mais le résultat de la simulation est différent, pas seulement sur la chronologie que j'ai voulue, Par exemple le résultat sum n'est pas toujours celui attendu. En fait c'est cur_blk qui ne contient plus la même chose. Le fait de mettre le enable_read d'une mémoire à 1 dans s0 ne garantit pas que la sortie sera valide à s1 ? Il faut attendre s2 ?