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-- Company:
-- Engineer:
--
-- Create Date: 17:42:33 05/08/2014
-- Design Name:
-- Module Name: note_pays - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity note_pays is
generic( p : integer := 5 );
port(
sel,CLK ,RAZ :in std_logic;
note_critere: in std_logic_vector( 3 downto 0);
n_p:inout std_logic_vector( p-1 downto 0)
);
end note_pays;
architecture Behavioral of note_pays is
begin
process(CLK,RAZ)
begin
if (CLK'event and CLK= '1') then
if ((RAZ = '1' ) and (sel='0')) then n_p <= "00000";
elsif ( ( RAZ ='0' ) and (sel='0') ) then n_p <= n_p;
elsif ( ((RAZ= '0') or (RAZ= '1')) and sel='1') then n_p <= n_p + note_critere;
end if;
end if;
end process ;
end Behavioral; |
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