Salut

J'ai fait un programme qui fait le calcul du PGCD en utilisant l'approche FSM+D
mais le programme s’exécute et le calcul du PGCD de deux entiers n'est pas correct.

SVP j'ai besoin d'aide pour faire fonctionner ce programme et merci d'avance.
Code :
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------------- Modélisation Niveau Dataflow (FSM+Datapath) du processeur PGCD -----------

-------------------------------------MULTIPLEXEUR --------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity multiplexeur is 
    port(	rst, sLine: in std_logic; 	load, result: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 3 downto 0 )        
	);
end multiplexeur;

architecture mux_fonctionnement of multiplexeur is
begin
    process( rst, sLine, load, result )
    begin
	if( rst = '1' ) then 
	    output <= "0000";		-- Rien
	elsif sLine = '0' then 
	    output <= load;		
	else 
	    output <= result;		
	end if;
    end process;
end mux_ fonctionnement;
	
---------------------------------------COMPARATEUR ---------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity comparateur is
    port(	rst: in std_logic;
		x, y: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 1 downto 0 )
    );
end comparateur;

architecture comp_fonctntionnemt of comparateur is
begin
    process( x, y, rst )
    begin
	if( rst = '1' ) then 
	    output <= "00";		-- Rien
	elsif( x > y ) then 
	    output <= "10";		-- si x est superieure
	elsif( x < y ) then 
	    output <= "01";		-- si y est superieure
	else 
	    output <= "11";  	        --  si egalité
	end if;
    end process;
end comp_fonctntionnemt;
----------------------------------- SOUSTRACTEUR ----------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity soustracteur is
    port (  rst: in std_logic;	cmd: in std_logic_vector( 1 downto 0 );
	x, y: in std_logic_vector( 3 downto 0 );	xout, yout: out std_logic_vector( 3 downto 0 )
           );
end soustracteur;

architecture soustraction of soustracteur is
begin
    process( rst, cmd, x, y )
    begin
	if( rst = '1' or cmd = "00" ) then 	-- inactif.
	    xout <= "0000";	
	    yout <= "0000";
	elsif( cmd = "10" ) then 		-- x est sup
	    xout <= ( x - y );
	    yout <= y;
	elsif( cmd = "01" ) then 		-- y est sup
	    xout <= x;	
	    yout <= ( y - x );
	else 
	    xout <= x;  			-- x et y égaux
	    yout <= y; 		
	end if;
    end process;
end soustraction;

------------------------------------------ REGISTRE-------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity registre is
    port(	rst, clk, load: in std_logic;        input: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 3 downto 0 )
    );
end registre;

architecture registre_fonctionnement of registre is
begin
    process( rst, clk, load, input )
    begin
	if( rst = '1' ) then 
	    output <= "0000";
	elsif( clk'event and clk = '1') then
	    if( load = '1' ) then	
	        output <= input;
	    end if;
        end if;
    end process;
end registre_fonctionnement;

--------------------------------- Contrôleur FSM  --------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity fsm is
    port(	rst, clk, go_i: in std_logic;
         x_lt_y,	x_neq_y : in std_logic;
		x_sel, y_sel, x_ld, y_ld,d_ld: out std_logic 
    );
end fsm;

architecture fsm_arc of fsm is

    type states is ( init, s00,s0, s1, s2, s3, s4, s5 ); -- les differents etats de notre FSM
    signal nState, cState: states; -- next state , et current state
    

begin
   
   process( rst, clk )
   begin
	if( rst = '1' ) then 
	    cState <= init;
	elsif( clk'event and clk = '1' ) then 
	    cState <= nState;
	end if;
   end process;

   
   process( go_i, x_lt_y, x_neq_y, cState )
   begin
        
	case cState is 
		
	when init =>	

	      if( go_i = '0' ) then 
			    nState <= init;
			else 
			    nState <= s00;
			end if;
			
	
	when s00 =>	d_ld<='0';
			x_sel <= '0';
			y_sel <= '0';
			x_ld <= '0';
			y_ld <= '0';
			nState <= s0;

   when s0 =>	d_ld<='0';
			x_sel <= '0';
			y_sel <= '0';
			x_ld <= '1';
			y_ld <= '1';
			nState <= s1;	
			
				
	when s1 => x_ld <='0';
	           y_ld <='0';
	          d_ld<='0';
	     if ( x_neq_y = '1' ) then
	         nState<= s2;
	     else nState<=s5;
		  end if;
		
	when s2 =>	x_ld <= '0';
           			y_ld <= '0';
			if( x_lt_y = '1' ) then 
			    nState <= s3;
			else 
			    nState <= s4; 	
			end if;
		
	when s3 =>	d_ld<='0';
			x_sel <= '0';
			y_sel <= '1';
			x_ld <= '0';
			y_ld <= '1';
			nState <= s1;
	
	when s4 =>	d_ld<='0';
			x_sel <= '1';
			y_sel <= '0';
			x_ld <= '1';
			y_ld <= '0';
			nState <= s1;

	when s5 =>	
			d_ld<='1';
			nState <= init;
			
	when others =>	nState <= s00;
			
        end case;
	
    end process;
	
end fsm_arc;



--------------------------------Composant principal PGCD (FSM+D) ----------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.all;

entity pgcd is
    port(	rst,clk,go_i: in std_logic;
		x_i, y_i: in std_logic_vector( 3 downto 0 );
		d_o: out std_logic_vector( 3 downto 0 )
    );
end pgcd;

architecture pgcd_arc of pgcd is

component fsm is
     port(	rst,clk,go_i: in std_logic;
		x_lt_y, x_neq_y: in std_logic;
		x_sel, y_sel, x_ld, y_ld, d_ld: out std_logic -- d_ld signal de fin 
    );
end component;

component mux is 
  port(	rst,sel: in std_logic; -- std_logic représente un bit
                               -- sLine = select line, soit x_sel ou y_sel
      val_init, result: in std_logic_vector( 3 downto 0 );
                                    
      output: out std_logic_vector( 3 downto 0 )
      );
end component;

component comparateur_neq is
   port(
		x, y: in std_logic_vector( 3 downto 0 ); -- les entrées à comparer
		x_neq_y: out std_logic -- le résultat de la comparaison, 1 si vrai, 0 sinon
    );
end component;

component comparateur_lt is
     port(	
		x, y: in std_logic_vector( 3 downto 0 ); -- les entrées à comparer
		x_lt_y: out std_logic -- le résultat de la comparaison, 1 si vrai, 0 sinon
    );
end component;

component soustracteur is
    port(	rst:in std_logic;
      x_lt_y: in std_logic; -- signal de commande
		x, y: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 3 downto 0 )
    );
end component;

component registre is
    port(	rst,clk,load: in std_logic; -- reset, horloge, signal load
	       input: in std_logic_vector( 3 downto 0 ); -- valeur d'entrée ex :x_i, résultat de la soustraction..
		    output: out std_logic_vector( 3 downto 0 ) -- valeur de sortie
    );
end component;

signal x_ld, y_ld, x_sel, y_sel, d_ld: std_logic;
signal x_lt_y,not_x_lt_y, x_neq_y: std_logic;
signal result: std_logic_vector( 3 downto 0 );					

signal xsub, ysub, xmux, ymux, xreg, yreg: std_logic_vector( 3 downto 0 );

begin
    not_x_lt_y <= not(x_lt_y);
    -- Controleur FSM 
    TOFSM: fsm port map(   rst,clk,go_i, x_lt_y, x_neq_y, 
			    x_sel, y_sel, x_ld, y_ld, d_ld );   				 
    -- Datapath
    X_MUX: mux port map( rst,x_sel, x_i, xsub, xmux );
    Y_MUX: mux port map( rst, y_sel, y_i, ysub, ymux );
    X_REG: registre port map(rst,clk,x_ld, xmux, xreg ); 
    Y_REG: registre port map(rst,clk,y_ld, ymux, yreg ); 
    neq_COMP: comparateur_neq port map( xreg, yreg, x_neq_y );
    lt_COMP: comparateur_lt port map( xreg, yreg, x_lt_y );
    Y_SUB: soustracteur port map( rst,x_lt_y, xreg, yreg, ysub );
    X_SUB: soustracteur port map( rst,not_x_lt_y, yreg, xreg, xsub );
    OUT_REG: registre port map( rst,clk,d_ld, xreg, result );
	
    d_o <= result; 

end pgcd_arc;