bonjour,

je souhaiterais créer une IP simple et l'ajouter comme périphérique sur le bus PLb (µblaze Xilinx), pour cela j'ai créé un compteur qui a comme entrée la valeur max à laquelle le compteur doit s'arrêter de compter et donc redémarrer a zéro, et en sortie la valeur du compteur.

sur l'interface esclave du PLB, j'ai créé deux registres, un pour val_compt_in et un autre pour val_compt_out, je doit être capable d'écrire sur le premier registre et de lire sur le deuxième......
le programme que j'ai élaboré ne fonctionne pas, je n'arrive pas a lire les registres:
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//user_logic

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_SLV_DWIDTH                   : integer              := 32;
    C_NUM_REG                      : integer              := 2
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
   --LEDs										: out std_logic_vector(0 to 7);
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute SIGIS : string;
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic

  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg_write_sel              : std_logic_vector(0 to 1);
  signal slv_reg_read_sel               : std_logic_vector(0 to 1);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;
-----------------------------------------------------------------------------------
  signal compt_out_sig						 : std_logic_vector(0 to 7);
  signal valeur_compt_sig						 : std_logic_vector(0 to 31);
  ---------------------------------------------------------------------------------
  
		 component compteur
						port(
						rst: std_logic;
						clk: in std_logic;
						valeur_compt: in std_logic_vector(0 to 31);
						compt_out: out std_logic_vector(0 to 7)
						);
					 end component;
begin

inst1: compteur 
		port map( 
		rst=>Bus2IP_Reset,
		clk=>Bus2IP_Clk,
		valeur_compt=>valeur_compt_sig,
		compt_out=>compt_out_sig
		);
		
  --USER logic implementation added here
	valeur_compt_sig<=slv_reg0; 
	slv_reg1(24 to 31)<=compt_out_sig;
--	LEDs<=compt_out_sig;
	slv_reg1(0 to 23)<=(others=>'0');

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  -- 
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic,
  -- you are basically operating on the following memory mapped registers:
  -- 
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  --                     "1000"   C_BASEADDR + 0x0
  --                     "0100"   C_BASEADDR + 0x4
  --                     "0010"   C_BASEADDR + 0x8
  --                     "0001"   C_BASEADDR + 0xC
  -- 
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 1);
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 1);
  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);

  -- implement slave model software accessible register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
        --slv_reg1 <= (others => '0');
      else
        case slv_reg_write_sel is
          when "10" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
				--when "01" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
						---slv_reg1<=slv_reg1;
--              end if;
--            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is
  begin

    case slv_reg_read_sel is
		when "10" => slv_ip2bus_data <= slv_reg0;
      when "01" => slv_ip2bus_data <= slv_reg1;---(others => '0'); -- il y avait a la place de '0' slv_reg1;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';

end IMP;
et le programme compteur est le suivant:

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entity compteur is
						port(
						rst: std_logic;
						clk: in std_logic;
						valeur_compt: in std_logic_vector(0 to 31);
						compt_out: out std_logic_vector(0 to 7)
						);
end compteur;

architecture Behavioral of compteur is

signal compt: std_logic_vector(0 to 31):=(others=>'0');

begin

process(clk)

	begin
	
		if rst='1' then
			
			compt_out<=(others=>'0');
			compt<=(others=>'0');--raz compteur
		
		elsif clk'event and clk='1' then
		
			if compt = valeur_compt then
				
				compt_out<=(others=>'0');
				compt<=(others=>'0');--raz compteur
			
			else
			
			compt_out<= compt(24 to 31);
			compt<=compt+1;
			
			end if;
			
			--compt<=compt+1;
		
		end if;
	
end process;
		
end Behavioral;
Merci d'avance de votre aide