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| LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
LIBRARY std;
USE std.textio.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY multiplication_tb IS
generic (N : integer:= 16);
END multiplication_tb;
ARCHITECTURE behavior OF multiplication_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplication
PORT(
clk : IN std_logic;
rst : IN std_logic;
en : IN std_logic;
AA : IN std_logic_vector(N downto 0);
BB : IN std_logic_vector(N downto 0);
SS : OUT std_logic_vector(2*N downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1';
signal rst : std_logic := '0';
signal en : std_logic := '1';
signal AA : std_logic_vector(N downto 0) := (others => '0');
signal BB : std_logic_vector(N downto 0) := (others => '0');
--Outputs
signal SS : std_logic_vector(2*N downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns; --10 ns;
--CONSTANT PERIOD : time := 12500 ps;
--files decleration
file signal1_vect : text open READ_MODE is "C:\Users\CHIHEB\Documents\MATLAB\data_in1.dat";
file signal2_vect : text open READ_MODE is "C:\Users\CHIHEB\Documents\MATLAB\data_in2.dat";
file signalout_vect : text open WRITE_MODE is "C:\Users\CHIHEB\Documents\MATLAB\data_out.dat";
--conversion functions decleration
--
FUNCTION str_to_stdvec(inp: string) return std_logic_vector is
VARIABLE temp: std_logic_vector(inp'range) := (others => 'X');
BEGIN
for i in inp'range loop
if (inp(i) = '1') then
temp(i) := '1';
elsif (inp(i) = '0') then
temp(i) := '0';
else temp(i) :='X';
end if;
end loop;
return temp;
end function str_to_stdvec;
--
FUNCTION stdvec_to_str(inp: std_logic_vector) return string is
VARIABLE temp: string(inp'left+1 downto 1) := (others => 'U');
BEGIN
for i in inp'reverse_range loop
if (inp(i) = '1') then
temp(i+1) := '1';
elsif (inp(i) = '0') then
temp(i+1) := '0';
else temp(i+1) := 'X';
end if;
end loop;
return temp;
end function stdvec_to_str;
--
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplication PORT MAP (
clk => clk,
rst => rst,
en => en,
AA => AA,
BB => BB,
SS => SS
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- ENABLE CLOCK DEF
ENABLE : process
begin
en <= not en;
wait for 10*clk_period/2;
end process ENABLE;
-- RESET CLOCK DEF
RESET : process
begin
rst <= transport '1';
wait for 7000 ps;
rst <= transport '0';
wait for 1000000 ns;
end process RESET;
--
-- -- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for clk_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
--
Read_input : process
variable str1_signal : string (N+1 downto 1);
variable file1_line : line;
variable str2_signal: string (N+1 downto 1);
variable file2_line : line;
begin
wait until rising_edge(Clk);
while not endfile(signal1_vect)and not endfile(signal2_vect)loop
readline(signal1_vect,file1_line);
readline(signal2_vect,file2_line);
read(file1_line,str1_signal);
read(file2_line,str2_signal);
wait for 1 ns;
AA <= str_to_stdvec(str1_signal);
BB <= str_to_stdvec(str2_signal);
wait until falling_edge(Clk);
end loop;
file_close(signal1_vect);
file_close(signal2_vect);
end process;
--
Write_output:process
variable temp_out: std_logic_vector (2*N downto 0);
variable outb: string (2*N+1 downto 1);
variable file_line : line;
begin
wait until falling_edge(Clk);
while not endfile(signal1_vect)and not endfile (signal2_vect)loop
wait for clk_period;
temp_out := SS;
outb := stdvec_to_str(temp_out);
write(file_line,outb);
writeline(signalout_vect,file_line);
end loop;
file_close(signalout_vect);
end process Write_output;
END behavior; |
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